LPS27HHW datasheet(36/60 Pages) STMICROELECTRONICS

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Digital interfaces

LPS27HHW

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DocID032730 Rev 1

7.5

I²C/MIPI I3CSM coexistence in LPS27HHW

In the LPS27HHW, the SDA and SCL lines are common to both I²C and MIPI I3CSM. The

I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with MIPI

I3CSM timing.

The device can be connected to both I²C and MIPI I3CSM or only to the MIPI I3CSM bus

depending on the connection of the INT1 pin when the device is powered up:



INT_DRDY pin floating (internal pull-down): I²C/MIPI I3CSM both active, see Figure 23

–

I²C case: INT_DRDY pin is by default an input with pull-down. If I²C is used,

INT_DRDY must be left unconnected or eventually pulled down during device

initialization. After power-on, during device configuration, the INT_DRDY pin can

be programmed as an interrupt output pin and it is recommended to set bit

I3C_disable to '1'.

–

I3C case: INT_DRDY pin is by default an input with pull-down. If I3C is used and

the INT_DRDY pin is unconnected, dynamic address assignment must be

performed using I²C Fast Mode Plus Timing (max 1 MHz clock). After dynamic

address assignment, I3C can be used in full speed mode.



INT_DRDY pin connected to VDD_IO: only MIPI I3CSM active, see Figure 24

–

Only I3C: INT_DRDY pin is by default an input with pull-down. If INT_DRDY is set

to Vdd_IO, I3C slave is selected and device can be initialized at full speed through

the SETDASA command. If the I3C bus is available for more than 10 msec and

the device is not yet addressed, a hot join request is performed (SDA line kept to

ground from slave) and the master must manage the request. After device

address assignment, a private write can be performed to disconnect the

INT_DRDY pull-down.

Figure 23. I²C and MIPI I3CSM both active (INT_DRDY pin not connected)

1. Address assignment (SETDASA) must be performed with I²C Fast Mode Plus Timing. When the slave is

addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications.

I²C/MIPI I3CSM

(both active)

Master sends

I²C r/w

I²C bus case

Slave performs

requested r/w

Master assigns DA

to the slave(1)

MIPI I3CSM bus case

MIPI I3CSM private R/W with and without

7EhCCC commands

Slave event management

Error detection and recovery

Master resets

INT_DRDY pin not connected

I²C/MIPI I3CSM both active

LPS27HHW Datasheet(PDF) 36 Page - STMicroelectronics

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