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SH79F3283P/044PR Datasheet(PDF) 57 Page - SINOWEALTH Electronic Ltd

Part # SH79F3283P/044PR
Description  Enhanced 8051 Microcontroller with 12bit ADC
PDF  144 Pages
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Manufacturer  SINOWEALTH [SINOWEALTH Electronic Ltd]
Direct Link  https://en.sinowealth.com
Logo SINOWEALTH - SINOWEALTH Electronic Ltd

SH79F3283P/044PR Datasheet(HTML) 57 Page - SINOWEALTH Electronic Ltd

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SH79F3283
57
7.9 Interrupt
7.9.1 Feature
 15 interrupt sources
 4 interrupt priority levels
The SH79F3283 provides total 15 interrupt sources: 5 external interrupts (INT0, INT1, INT2, INT3, INT4), INT4 has 8 interrupt
sources (INT40-47, which share the same vector address), 4 timer interrupts (Timer2, 3, 4, 5), two EUART interrupt, SPI
interrupt, ADC Interrupt, PWM interrupts, SCM interrupt and LPD interrupt.
7.9.2 Interrupt Enable Control
Each interrupt source can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt
enable registers IEN0 or IEN1. The IEN0 register also contains global interrupt enable bit, EA, which can enable/disable all the
interrupts at once. Generally, after reset, all interrupt enable bits are set to 0, which means that all the interrupts are disabled.
7.9.3 Register
Table 7.39 Primary Interrupt Enable Register
A8H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IEN0
EA
EADC
ET2
ES0
-
EX1
ET5
EX0
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
0
0
-
0
0
0
Bit Number
Bit Mnemonic
Description
7
EA
All interrupt enable bit
0: Disable all interrupt
1: Enable all interrupt
6
EADC
ADC interrupt enable bit
0: Disable ADC interrupt
1: Enable ADC interrupt
5
ET2
Timer2 overflow interrupt enable bit
0: Disable Timer2 overflow interrupt
1: Enable Timer2 overflow interrupt
4
ES0
EUART0 interrupt enable bit
0: Disable EUART0 interrupt
1: Enable EUART0 interrupt
2
EX1
External interrupt1 enable bit
0: Disable external interrupt1
1: Enable external interrupt1
1
ET5
Timer5 overflow interrupt enable bit
0: Disable Timer5 overflow interrupt
1: Enable Timer5 overflow interrupt
0
EX0
External interrupt0 enable bit
0: Disable external interrupt0
1: Enable external interrupt0



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