SH79F3283PSLASH044PR datasheet(64/144 Pages) SINOWEALTH

64 / 144 page

SH79F3283

7.9.9 External Interrupt Inputs

The SH79F3283 has 5 external interrupt inputs. External interrupt0-3 each has one vector address. External interrupt 4 has 8

inputs; all of them share one vector address. These external interrupts can be programmed to be level-triggered or

edge-triggered by clearing or setting bit IT1 or IT0 in register TCON and register EXF1. If ITn = 0 (n = 0 - 1), external interrupt

0/1 is triggered by a low level detected at the INT0/1 pin. If ITn = 1 (n = 0 - 1), external interrupt 0/1 is edge triggered. In this

mode if consecutive samples of the INT0/1 pin show a high level in one cycle and a low level in the next cycle, interrupt

request flag in register r EXF1 is set, causing an interrupt request. Since the external interrupt pins are sampled once each

machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling.

If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle,

and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request

flag is set. Notice that IE0-1 is automatically cleared by CPU when the service routine is called while IF4x should be cleared by

software. External interrupt4 operates in the similar ways except have different registers and have more selection of trigger.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is

generated, which will take 2 machine cycles. If the external interrupt is still asserted when the interrupt service routine is

completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEx (x = 0, 1, 2, 3) when the

interrupt is level sensitive, it simply tracks the input pin level.

In order to satisfy the different request interrupt response, there can set sample clock Prescaler Select bits and sample times

Select bits in EXCON register

Sample clock Prescaler Select bits and sample times Select bits in EXCON register are invalid in the IDLE and Power-Down

mode.

If an external interrupt is enabled when the SH79F3283 is put into Power down or Idle mode, the interrupt occurrence will

cause the processor to wake up and resume operation.

IEi

The Block Diagram of INTi

Interrupt

Request

Flag

System Clock

IxSN[1:0],x=0,1

INTi

PxCR

x=0,2,3,4

Sampling

ITi[1:0], i=2-4

ITi[1:0], i=0-1

Sampling Num

1,2,3,4

Prescaler

1,4,16,64

IxPS[1:0],x=0,1

Note: The INT0/1/2/3 interrupt flag will be cleared by hardware, but IF40-IF47 must be cleared by software

SN Sampling Cyle

> SN Sampling Cycle

High-Level Threshold

Low-Level Threshold

>2*SN Sampling Cycle

(SN=1,2,3,4)

External Interrupt Detecting

SH79F3283P/044PR Datasheet(PDF) 64 Page - SINOWEALTH Electronic Ltd

SH79F3283P/044PR Datasheet(HTML) 64 Page - SINOWEALTH Electronic Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL