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STA350B Datasheet(PDF) 84 Page - STMicroelectronics

Part # STA350B
Description  2.1-channel high-efficiency digital audio system Sound TerminalR
PDF  94 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA350B Datasheet(HTML) 84 Page - STMicroelectronics

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STA350B, STA350BW
84/94
DocID018572 Rev 7
In this case the user can decide, for each filter stage, the right coefficients range. Note that
for a given biquad the same range will be applied to Left and Right (Channel 1 and Channel
2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1)
range unchanged.
8.24
Miscellaneous registers (address 0x4B, 0x4C)
8.24.1
Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA350Bx, by default, the power-down pin and I2C power-down act on mute
commands to perform the fadeout. This default can be changed so that the fadeout can be
started using the master volume. The RPDNEN bit, when set, activates this feature.
8.24.2
Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B,
bit D6)
Following the description in Section 8.22, this bit, when set, enables the noise-shaping
technique on the DC cutoff filter. Channels 1 and 2 share the same settings.
8.24.3
Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)
A fadeout procedure is started in the STA350Bx once the PWDN function is enabled.
Independently from the fadeout time, after 13 million clock cycles (PLL internal frequency)
the bridge is put in powerdown (tri-state mode). There is also the possibility to change this
behavior so that the power bridge will be switched off immediately after the PWDN pin is tied
to ground, without therefore waiting for the 13 million clock cycles. The BRIDGOFF bit,
when set, activates this function. Obviously the immediate power-down will generate a pop
noise at the output. therefore this procedure must be used only in case pop noise is not
relevant in the application. Note that this feature works only for hardware PWDN assertion
and not for a powerdown applied through the I2C interface. Refer to Section 8.24.5 in order
to program a different number of clock cycles.
D7
D6
D5
D4
D3
D2
D1
D0
RPDNEN
NSHHPEN
BRIDGOFF
Reserved
Reserved
CPWMEN
Reserved
Reserved
0
0
00
01
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
Reserved
PNDLSL[2]
PNDLSL[1]
PNDLSL[0]
Reserved
Reserved
0
0
00
00
0
0



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