STA350B datasheet(42/94 Pages) STMICROELECTRONICS

42 / 94 page

STA350B, STA350BW

42/94

DocID018572 Rev 7

To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any

audio streams flowing into the STA350Bx data path before the desynchronize event

happens. At the same time any processing related to the I2C configuration should be issued

only after the serial audio interface and the internal PLL are synchronous again.

Note:

Any mute or volume change causes some delay in the completion of the I2C operation due

to the soft-volume feature. The soft-volume phase change must be finished before any clock

desynchronization.

8.2.4

Delay serial clock enable

8.2.5

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers map each I2S input channel to its corresponding processing

channel.

Table 20. Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: No serial clock delay

1: Serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 21. Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

C1IM

0: Processing channel 1 receives Left I2S Input

1: Processing channel 1 receives Right I2S Input

7R/W

C2IM

0: Processing channel 2 receives Left I2S Input

1: Processing channel 2 receives Right I2S Input

STA350B Datasheet(PDF) 42 Page - STMicroelectronics

STA350B Datasheet(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL