STGIPN3HD60-H datasheet(10/21 Pages) STMICROELECTRONICS

10 / 21 page

Table 10. Logic inputs

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Vil

Low logic level voltage

0.8

Vih

High logic level voltage

2.25

IHINh

HIN logic “1” input bias

current

HIN = 15 V

100

µA

IHINl

HIN logic “0” input bias

current

HIN = 0 V

µA

ILINl

LIN logic “0” input bias current LIN = 0 V

µA

ILINh

LIN logic “1” input bias current LIN = 15 V

100

µA

ISDh

SD logic “0” input bias current SD = 15 V

120

300

µA

ISDl

SD logic “1” input bias current SD = 0 V

µA

Dead time

see Figure 5. Dead time and

interlocking waveform

definitions

360

Table 11. Op-amp characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Vio

Input offset voltage

Vic = 0 V, Vo = 7.5 V

Iio

Input offset current

Vic = 0 V, Vo = 7.5 V

Iib

Input bias current (1)

100

200

VOL

Low level output voltage

RL = 10 kΩ to VCC

150

VOH

High level output voltage

RL = 10 kΩ to GND

14.7

Output short-circuit current

Source, Vid = + 1 V, Vo = 0 V

Sink, Vid = -1 V, Vo = VCC

Slew rate

Vi = 1 - 4 V, CL = 100 pF, unity

gain

2.5

3.8

V/µs

GBWP

Gain bandwidth product

Vo = 7.5 V

MHz

Avd

Large signal voltage gain

RL = 2 kΩ

SVR

Supply voltage rejection ratio

vs. VCC

CMRR

Common mode rejection ratio

1. The direction of input current is out of the IC.

STGIPN3HD60-H

Control part

DS11784 - Rev 3

page 10/21

STGIPN3HD60-H Datasheet(PDF) 10 Page - STMicroelectronics

STGIPN3HD60-H Datasheet(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datasheet Download

Link URL