STM32L010R8 datasheet(19/92 Pages) STMICROELECTRONICS

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DS12325 Rev 3

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STM32L010K8 STM32L010R8

Functional overview

3.5

Clock management

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. Its associated features are the listed below:

•

Clock prescaler

To get the best trade-off between speed and current consumption, the clock frequency

to the CPU and peripherals can be adjusted by a programmable prescaler.

•

Safe clock switching

Clock sources can be changed safely on the fly in Run mode through a configuration

•

Clock management

To reduce power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory.

•

System clock source

Three different clock sources are available to drive the master clock SYSCLK:

–

0-32 MHz high-speed external (HSE), that can supply a PLL

–

16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLL

–

multispeed internal RC oscillator (MSI), trimmable by software, able to generate

seven frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz

and 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),

the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

•

Auxiliary clock source

Two ultra-low-power clock sources can be used to drive the real-time clock:

–

32.768 kHz low-speed external crystal (LSE)

–

37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for

greater precision.

•

RTC clock sources

The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system

clock.

•

Startup clock

After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).

The prescaler ratio and clock source can be changed by the application program as

soon as the code execution starts.

•

Clock security system (CSS)

This feature can be enabled by software. If an LSE clock failure occurs, it provides an

interrupt or wakeup event that is generated assuming it has been previously enabled.

This feature is not available on the HSE clock.

•

Clock-out capability (MCO: microcontroller clock output)

It outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and

APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz.

See Figure 2 for details on the clock tree.

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