MPC8540 datasheet(51/1302 Pages) FREESCALE

51 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

13-82

Interface to MSC8102 DSI in Asynchronous Mode ......................................................... 13-108

13-83

Asynchronous Write to MSC8102 DSI............................................................................. 13-109

13-84

Asynchronous Read from MSC8102 DSI......................................................................... 13-110

13-85

Interface to MSC8102 DSI in Synchronous Mode ............................................................13-111

13-86

UPM Synchronization Cycle ............................................................................................ 13-112

13-87

Synchronous Single Write to MSC8102 DSI.................................................................... 13-114

13-88

Synchronous Single Read from MSC8102 DSI................................................................ 13-115

13-89

Synchronous Burst Write to MSC8102 DSI ..................................................................... 13-116

13-90

Synchronous Burst Read from MSC8102 DSI ................................................................. 13-117

13-91

Interface to Texas Instruments EHPI in Non-Multiplexed Mode ..................................... 13-120

13-92

EHPI Non-Multiplexed Read Timings.............................................................................. 13-121

13-93

EHPI Non-Multiplexed Write Timings ............................................................................. 13-121

14-1

Ethernet Protocol in Relation to the OSI Protocol Stack ...................................................... 14-2

14-2

IEEE 802.3z and 802.3ab Physical Standards ...................................................................... 14-3

14-3

Ethernet/IEEE 802.3 Frame Structure .................................................................................. 14-3

14-4

Ethernet/IEEE 802.3 Frame Structure With More Details.................................................... 14-5

14-5

TSEC Block Diagram ........................................................................................................... 14-6

14-6

IEVENT Register Definition .............................................................................................. 14-21

14-7

IMASK Register Definition ................................................................................................ 14-23

14-8

Error Disabled Register (EDIS) .......................................................................................... 14-24

14-9

ECNTRL Register Definition ............................................................................................. 14-25

14-10

MINFLR Register Definition.............................................................................................. 14-26

14-11

PTV Register Definition...................................................................................................... 14-27

14-12

DMACTRL Register Definition ......................................................................................... 14-28

14-13

TBIPA Register Definition.................................................................................................. 14-29

14-14

FIFO_PAUSE_CTRL Register Definition......................................................................... 14-31

14-15

FIFO_TX_THR Register Definition ................................................................................... 14-31

14-16

FIFO_TX_STARVE Register Definition ............................................................................ 14-32

14-17

FIFO_TX_STARVE_SHUTOFF Register Definition ........................................................ 14-33

14-18

TCTRL Register Definition ................................................................................................ 14-33

14-19

TSTAT Register Definition ................................................................................................. 14-34

14-20

TBDLEN Register Definition ............................................................................................. 14-35

14-21

TXIC Register Definition.................................................................................................... 14-35

14-22

CTBPTR Register Definition .............................................................................................. 14-36

14-23

TBPTR Register Definition................................................................................................. 14-37

14-24

TBASE Register Definition ................................................................................................ 14-38

14-25

OSTBD Register Definition................................................................................................ 14-38

14-26

OSTBDP Register Definition.............................................................................................. 14-40

14-27

RCTRL Register Definition ................................................................................................ 14-41

14-28

RSTAT Register Definition ................................................................................................. 14-42

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