MPC8540 datasheet(96/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-2

Freescale Semiconductor

Overview

Figure 1-1. MPC8540 Block Diagram

1.2.1

Key Features

The following is an overview of the MPC8540 feature set:

•

High-performance, 32-bit Book E–enhanced core that implements the PowerPC

architecture

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection.

Caches can be locked entirely or on a per-line basis, with separate locking for

instructions and data.

— Signal-processing engine (SPE) auxiliary processing unit (APU) provides an extensive

instruction set for vector (64-bit) integer, single-precision floating-point, and fractional

operations. These instructions use both the upper and lower words of the 64-bit GPRs

as they are defined by the SPE APU.

— The single-precision floating-point (SPFP) APU provides an instruction set for

single-precision (32-bit) floating-point instructions.

— Memory management unit (MMU) especially designed for embedded applications

— Enhanced hardware and software debug support

— Performance monitor facility (similar to but different from the MPC8540 performance

monitor described in Chapter 19, “Performance Monitor.”)

Core Complex

16 Gb/s

RapidIO-8

133 MHz

PCI-X 64b

10/100/1Gb

MII, GMII,TBI,

RTBI, RGMII

MII, GMII,TBI,

RTBI, RGMII

MII

Serial

IRQs

SDRAM

DDR

ROM,

10/100/1Gb

SDRAM,

GPIO

Bus

I2C

TSEC

I2C

Interface

TSEC

PCI/PCI-X Bus

Interface

e500

Coherency

Module

DDR Memory Controller

Local Bus Controller

Programmable Interrupt

Controller

DUART

e500 Core

256-Kbyte

L2 Cache/

SRAM

4-Channel DMA

Controller

10/100 Fast

Ethernet Controller

32-Kbyte L1

Instruction

Cache

32-Kbyte

L1 Data

Cache

OCeaN

Switch

Fabric

RapidIO Interface

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