MPC8540 datasheet(179/1302 Pages) FREESCALE

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Signals Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

3-11

IRQ_OUT

Interrupt output

PIC

—

10-6/10-8

L1_TSTCLK

L1 test clock

Test

—

20-2/20-6

L2_TSTCLK

L2 test clock

Test

—

20-2/20-6

LA27

LBC burst address

LBC

cfg_cpu_boot

13-1/13-5

LAD[0:31]

LBC address/data

LBC

cfg_gpporcr

I/O

13-1/13-5

LALE

LBC address latch enable

LBC

cfg_core_pll0

13-1/13-5

LA[28:31]

LBC port address

LBC

cfg_sys_pll0

cfg_sys_pll1

cfg_sys_pll2

cfg_sys_pll3

13-1/13-5

LBCTL

LBC data buffer control

LBC

—

13-1/13-5

LCKE

LBC clock enable

LBC

—

13-1/13-5

LCLK[0:2]

LBC clock

LBC

—

13-1/13-5

LCS5

LBC chip select 5

LBC

DMA_DREQ2

13-1/13-5

LCS6

LBC chip select 6

LBC

DMA_DACK2

13-1/13-5

LCS7

LBC chip select 7

LBC

DMA_DDONE2

13-1/13-5

LCS[0:4]

LBC Chip select 0–4

LBC

—

13-1/13-5

LDP[0:3]

LBC data parity

LBC

—

I/O

13-1/13-5

LGPL0/LSDA10

LBC UPM general

purpose line 0/SDRAM

address bit 10

LBC

cfg_rio_clk0

13-1/13-5

LGPL1/LSDWE

LBC GP line 1/SDRAM

write enable

LBC

cfg_rio_clk1

13-1/13-5

LGPL2/LOE/

LSDRAS

LBC GP line 2/output

enable/SDRAM RAS

LBC

cfg_core_pll1

13-1/13-5

LGPL3/LSDCAS

LBC GP line 3/SDRAM

CAS

LBC

cfg_boot_seq0

13-1/13-5

LGPL4/LGTA/

LUPWAIT/LPBSE

LBC GP line 4/GPCM

terminate access/UPM

wait/parity byte select

LBC

—

I/O

13-1/13-5

LGPL5

LBC GP line 5 address

LBC

cfg_boot_seq1

13-1/13-5

LSSD_MODE

LSSD mode

Test

—

20-2/20-6

LSYNC_IN,

LSYNC_OUT

LBC DLL synchronization

LBC

—

I/O

13-1/13-5

LWE[0:1]/

LSDDQM[0:1]/

LBS[0:1]

LBC write enable/byte

lane data mask/byte

select 0–1

LBC

cfg_pci_hold[0:1]

13-1/13-5

Table 3-2. MPC8540 Alphabetical Signal Reference (continued)

Name

Description

Functional

Block

Alternate

Function(s)

No. of

Signals

I/O

Table/

Page

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