DP83848-HT datasheet(39/81 Pages) TI

39 / 81 page

MDC

MDIO

(STA)

Idle

Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

Idle

DP83848-HT

www.ti.com

SLLSEJ7 – FEBRUARY 2015

Figure 37. Typical MDC/MDIO Write Operation

8.4.4.3 Serial Management Preamble Suppression

The DP83848 supports a preamble suppression mode as indicated by a one in bit 6 of the basic mode status

determines that all PHYs in the system support preamble suppression by returning a one in this bit, then the

station management entity need not generate preamble for each management transaction.

The DP83848 requires a single initialization sequence of 32 bits of preamble following hardware/software reset.

This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous

MDC, or the management access made to determine whether preamble suppression is supported.

While the DP83848 requires an initial preamble sequence of 32 bits for management initialization, it does not

require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between

management transactions is required as specified in the IEEE 802.3u specification.

8.5 Programming

8.5.1 Auto-Negotiation

The auto-negotiation function provides a mechanism for exchanging configuration information between two ends

of a link segment and automatically selecting the highest performance mode of operation supported by both

devices. Fast link pulse (FLP) bursts provide the signalling used to communicate auto-negotiation abilities

between two devices at each end of a link segment. For further detail regarding auto-negotiation, refer to Clause

28 of the IEEE 802.3u specification. The DP83848 supports four different ethernet protocols (10 Mb/s half

duplex, 10 Mb/s full duplex, 100 Mb/s half duplex, and 100 Mb/s full duplex), so the inclusion of auto-negotiation

ensures that the highest performance protocol will be selected based on the advertised ability of the link partner.

The auto-negotiation function within the DP83848 can be controlled either by internal register access or by the

use of the AN_EN, AN1 and AN0 pins.

8.5.1.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 and AN1 determines whether the DP83848 is forced into a specific mode or auto-

negotiation will advertise a specific ability (or set of abilities) as given in Table 33. These pins allow configuration

options to be selected without requiring internal register access.

The state of AN_EN, AN0 and AN1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register.

The auto-negotiation function selected at power-up or reset can be changed at any time by writing to the basic

mode control register (BMCR) at address 0x00h.

Table 33. Auto-Negotiation Modes

AN_EN

AN1

AN0

Forced Mode

10BASE-T, Half Duplex

10BASE-T, Full Duplex

100BASE-TX, Half Duplex

100BASE-TX, Full Duplex

AN_EN

AN1

AN0

Advertised Mode

10BASE-T, Half or Full Duplex

100BASE-TX, Half or Full Duplex

Submit Documentation Feedback

Product Folder Links: DP83848-HT

DP83848-HT Datasheet(PDF) 39 Page - Texas Instruments

DP83848-HT Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL