DP83848-HT datasheet(60/81 Pages) TI

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DP83848-HT

SLLSEJ7 – FEBRUARY 2015

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8.6.3.7 RMII and Bypass Register (RBR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is

bypassed.

Table 53. RMII and Bypass Register (RBR), Addresses 0x17

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:6

RESERVED

0, RO

Reserved: Writes ignored, Read as 0

Reduced MII Mode:

RMII_MODE

Strap, RW

0 = Standard MII Mode

1 = Reduced MII Mode

Reduce MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to

RMII_REV1_0

0, RW

indicate deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is

transferred. CRS_DV will not toggle at the end of a packet.

RX FIFO Over Flow Status:

RX_OVF_STS

0, RO

0 = Normal

1 = Overflow detected

RX FIFO Under Flow Status:

RX_UNF_STS

0, RO

0 = Normal

1 = Underflow detected

Receive Elasticity Buffer:

This field controls the Receive Elasticity Buffer which allows for

frequency variation tolerance between the 50MHz RMII clock and the

recovered data. The following values indicate the tolerance in bits for

a single packet. The minimum setting allows for standard Ethernet

frame sizes at ±50ppm accuracy for both RMII and Receive clocks.

For greater frequency tolerance the packet lengths may be scaled (i.e.

1:0

ELAST_BUF[1:0]

01, RW

for ±100ppm, the packet lengths need to be divided by 2).

00 = 14 bit tolerance (up to 16800 byte packets)

01 = 2 bit tolerance (up to 2400 byte packets)

10 = 6 bit tolerance (up to 7200 byte packets)

11 = 10 bit tolerance (up to 12000 byte packets)

8.6.3.8 LED Direct Control Register (LEDCR)

This register provides the ability to directly control any or all LED outputs. It does not provide read access to

LEDs.

Table 54. LED Direct Control Register (LEDCR), Address 0x18

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:6

RESERVED

0, RO

Reserved: Writes ignored, Read as 0

1 = Drive value of SPDLED bit onto LED_SPD output

DRV_SPDLED

0, RW

0 = Normal operation

1 = Drive value of LNKLED bit onto LED_LNK output

DRV_LNKLED

0, RW

0 = Normal operation

1 = Drive value of ACTLED bit onto LED_ACT/COL output

DRV_ACTLED

0, RW

0 = Normal operation

SPDLED

0, RW

Value to force on LED_SPD output

LNKLED

0, RW

Value to force on LED_LNK output

ACTLED

0, RW

Value to force on LED_ACT/COL output

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