ISL68229IRAZ datasheet(29/107 Pages) RENESAS

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ISL68229, ISL68239

6. Fault Monitoring and Protection

R16DS0006EU0101 Rev.1.01

Page 29 of 106

Jul 21, 2022

Fault Monitoring and Protection

The ISL68229 and ISL68239 include an extensive fault management system that integrates with high

performance host controllers, supporting unprecedented remote system management and debugging capability. If

a fault condition occurs, the IC deasserts the PG pin associated with the faulted rail and alerts the host using the

PMAlert pin. You can optionally configure the Catastrophic Failure Protection (CFP) to assert on select faults for

additional protection measures at the system level. The ISL68229 and ISL68239 also provide Black Box, a

recorder with extensive fault logging to support system level debug.

Fault controls are independently enabled and associated fault responses are user configurable. Response type is

independently configurable by fault type. Response types supported are:

• Alert only: The rail continues to operate.

• Shut down immediately: The rail is latched off until commanded on.

• Shut down and retry with variable retry delay: The rail attempts to retry indefinitely until the condition clears

or the rail is commanded off.

When a fault condition has been declared, clear the fault by issuing a CLEAR_FAULTS (03h) command or by

cycling the EN pin of the faulted rail.

6.1

Power-Good Signals

The PG pins are open-drain, power-good outputs that indicate completion of the soft-start sequence and output

voltage of the associated rail within the expected regulation range. If a fault occurs, the PG pin of the associated

rail is pulled low. PG is also pulled low immediately upon a rail disable.

6.2

Overvoltage/Undervoltage Protection

Output voltage is measured at the load sensing points differentially for regulation, and the same measurement is

used for OVP and UVP. The fault thresholds are set using PMBus commands. Figure 19 shows a simplified

OVP/UVP block diagram. The output voltage comparisons are done in the digital domain.

The device responds to an output overvoltage condition by disabling the output, declaring a fault, setting the

PMALERT pin, pulling the PG pin low, and then pulsing the LFET until the output voltage drops below the

threshold. Similarly, the device responds to an output undervoltage condition by disabling the output, declaring a

fault, setting the PMALERT pin, and pulling the PG pin low. The output does not restart until the EN pin is cycled

(unless the device is configured to retry).

In addition, the ISL68229 and ISL68239 feature open pin sensing protection to detect an open of the output

voltage sensing circuit. When this condition is detected, controller operation is suspended.

Figure 19. OVP, UVP Comparators

ISL68229IRAZ Datasheet(PDF) 29 Page - Renesas Technology Corp