ADC12DL080 datasheet(18/24 Pages) NSC

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Functional Description

Operating on a single +3.3V supply, the ADC12DL080 uses

a pipeline architecture and has error correction circuitry to

help ensure maximum performance. The differential analog

input signal is digitized to 12 bits. The user has the choice of

using an internal 1.0 Volt or an external reference. Any

external reference is buffered on-chip to ease the task of

driving that pin.

The output word rate is the same as the clock frequency,

which can be between 10 MSPS and 80 MSPS (typical) with

fully specified performance at 80 MSPS. The analog input for

both channels is acquired at the rising edge of the clock and

the digital data for a given sample is delayed by the pipeline

for 7 clock cycles. Duty cycle stabilization and output data

format are selectable. The output data format can be set for

offset binary or two’s complement.

A logic high on the power down (PD) pin reduces the con-

verter power consumption to 50 mW.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC12DL080:

3.0V

≤ V

≤ 3.6V

D =VA

2.4V

≤ V

10 MHz

≤ f

CLK

≤ 80 MHz

0.8V

≤ V

REF

≤ 1.2V (for an external reference)

1.0V

≤ V

≤ 2.0V

1.1 Analog Inputs

There is one reference input pin, V

REF, which is used to

select an internal reference, or to supply an external refer-

ence. The ADC12DL080 has two analog signal input pairs,

IN A+ and VIN A- for one converter and VIN B+ and VIN B-

for the other converter. Each pair of pins forms a differential

input pair.

1.2 Reference Pins

The ADC12DL080 is designed to operate with an internal

1.0V reference or an external 1.0V reference, but performs

well with external reference voltages in the range of 0.8V to

1.2V. Lower reference voltages will decrease the signal-to-

noise ratio (SNR) of the ADC12DL080. Increasing the refer-

ence voltage (and the input signal swing) beyond 1.2V may

degrade THD for a full-scale input, especially at higher input

frequencies.

It is important that all grounds associated with the reference

voltage and the analog input signal make connection to the

ground plane at a single, quiet point to minimize the effects

of noise currents in the ground path.

The six Reference Bypass Pins (V

RPA, VRMA, VRNA, VRPB,

RMB and VRNB) are made available for bypass purposes.

All these pins should each be bypassed to ground with a 0.1

µF capacitor. A 10 µF capacitor should be placed between

the V

RPA and VRNA pins and between the VRPB and VRNB

pins, as shown in Figure 4. This configuration is necessary to

avoid reference oscillation, which could result in reduced

SFDR and/or SNR.

Smaller capacitor values than those specified will allow

faster recovery from the power down mode, but may result in

degraded noise performance. Loading any of these pins

other than V

RMA and VRMB may result in performance deg-

radation.

The nominal voltages for the reference bypass pins are as

follows:

RM = 1.5 V

RP =VRM +VREF /2

RN =VRM −VREF /2

User choice of an on-chip or external reference voltage is

provided. The internal 1.0 Volt reference is in use when the

the V

REF pin is connected to VA. If a voltage in the range of

0.8V to 1.2V is applied to the V

REF pin, that is used for the

voltage reference. When an external reference is used, the

REF pin should be bypassed to ground with a 0.1 µF ca-

pacitor close to the reference input pin. There is no need to

bypass the V

REF pin when the internal reference is used.

1.3 Signal Inputs

The signal inputs are V

IN A+ and VINA− for one ADC and

INB+ and VINB− for the other ADC . The input signal, VIN,is

defined as

IN A= (VINA+) – (VINA−)

for the "A" converter and

IN B=(VINB+) – (VINB−)

for the "B" converter. Figure 2 shows the expected input

signal range. Note that the common mode input voltage,

CM, should be in the range of 1.0V to 2.0V.

The peaks of the individual input signals should never ex-

ceed 2.6V.

The ADC12DL080 performs best with a differential input

signal with each input centered around a common mode

voltage, V

CM. The peak-to-peak voltage swing at each ana-

log input pin should not exceed the value of the reference

voltage or the output data will be clipped.

The two input signals should be exactly 180˚ out of phase

from each other and of the same amplitude. For single

frequency inputs, angular errors result in a reduction of the

effective full scale input. For complex waveforms, however,

angular errors will result in distortion.

For single frequency sine waves the full scale error in LSB

can be described as approximately

FS =4096(1-sin (90˚ + dev))

Where dev is the angular difference in degrees between the

two signals having a 180˚ relative phase relationship to each

other (see Figure 3). Drive the analog inputs with a source

impedance less than 100

Ω.

20169411

FIGURE 2. Expected Input Signal Range

ADC12DL080 Datasheet(PDF) 18 Page - National Semiconductor (TI)

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