ADC12DL080 datasheet(19/24 Pages) NSC

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Applications Information (Continued)

For differential operation, each analog input pin of the differ-

ential pair should have a peak-to-peak voltage equal to the

reference voltage, V

REF, be 180 degrees out of phase with

each other and be centered around V

CM.

1.3.1 Single-Ended Operation

Performance with differential input signals is better than with

single-ended signals. For this reason, single-ended opera-

tion is not recommended. However, if single ended-operation

is required and the resulting performance degradation is

acceptable, one of the analog inputs should be connected to

the d.c. mid point voltage of the driven input. The peak-to-

peak input signal at the driven input pin should be twice the

reference voltage to maximize SNR and SINAD performance

(Figure 2b). For example, set V

REF to 1.0V, bias VIN− to 1.5V

and drive V

IN+ with a signal range of 0.5V to 2.5V.

Because very large input signal swings can degrade distor-

tion performance, better performance with a single-ended

input can be obtained by reducing the reference voltage

when maintaining a full-range output. Table 1 and Table 2

indicate the input to output relationship of the ADC12DL080.

TABLE 1. Input to Output Relationship – Differential

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF/2

CM +

REF/2

0000 0000 0000

1000 0000 0000

CM −

REF/4

CM +

REF/4

0100 0000 0000

1100 0000 0000

1000 0000 0000

0000 0000 0000

CM +

REF/4

CM −

REF/4

1100 0000 0000

0100 0000 0000

CM +

REF/2

CM −

REF/2

1111 1111 1111

0111 1111 1111

TABLE 2. Input to Output Relationship – Single-Ended

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF

0000 0000 0000

1000 0000 0000

CM −

REF/2

0100 0000 0000

1100 0000 0000

IN+

IN−

Binary Output

2’s Complement

Output

1000 0000 0000

0000 0000 0000

CM +

REF/2

1100 0000 0000

0100 0000 0000

CM +

REF

1111 1111 1111

0111 1111 1111

1.3.2 Driving the Analog Inputs

The V

IN+ and the VIN− inputs of the ADC12DL080 consist of

an analog switch followed by a switched-capacitor amplifier.

As the internal sampling switch opens and closes, current

pulses occur at the analog input pins, resulting in voltage

spikes at the signal input pins. As the driving source attempts

to counteract these voltage spikes, it may add noise to the

signal at the ADC analog input. To help isolate the pulses at

the ADC input from the amplifier output, use RCs at the

inputs, as can be seen in Figure 4 and Figure 5. These

components should be placed close to the ADC inputs be-

cause the input pins of the ADC is the most sensitive part of

the system and this is the last opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC

sample rate. The ADC input capacitance in the sample mode

should be considered when setting the RC pole. For wide-

band undersampling applications, the RC pole should be set

at about 1.5 to 2 times the maximum input frequency to

maintain a linear delay response. The values of the RC

shown in Figure 4 and Figure 5 are suitable for applications

with input frequencies up to approximately 70MHz.

1.3.3 Input Common Mode Voltage

The input common mode voltage, V

CM, should be in the

range of 1.0V to 2.0V and be a value such that the peak

excursions of the analog signal does not go more negative

than ground or more positive than 2.6V. See Section 1.2

2.0 DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK,

REFSEL/DCS, OF/DOEN, OEA/OF, OEB/DRDY. The OEB/

DRDY pin may also be configured as the DRDY output.

2.1 CLK

The CLK signal controls the timing of the sampling process.

Drive the clock input with a stable, low jitter clock signal in

the range of 10 MHz to 80 MHz. The higher the input

frequency, the more critical it is to have a low jitter clock. The

trace carrying the clock signal should be as short as possible

and should not cross any other signal line, analog or digital,

not even at 90˚.

The CLK signal also drives an internal state machine. If the

CLK is interrupted, or its frequency too low, the charge on

internal capacitors can dissipate to the point where the ac-

curacy of the output data will degrade. This is what limits the

lowest sample rate.

The clock line should be terminated at its source in the

characteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on

setting characteristic impedance.

It is highly desirable that the the source driving the ADC CLK

pin only drive that pin. However, if that source is used to

drive other things, each driven pin should be a.c. terminated

20169412

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level or Cause

Distortion

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