ADC12DL080 datasheet(23/24 Pages) NSC

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Applications Information (Continued)

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any

external component (e.g., a filter capacitor) connected be-

tween the converter’s input pins and ground or to the refer-

ence input pin and ground should be connected to a very

clean point in the ground plane.

Figure 6 gives an example of a suitable layout. All analog

circuitry (input amplifiers, filters, reference components, etc.)

should be placed in the analog area of the board. All digital

circuitry and I/O lines should be placed in the digital area of

the board. The ADC12DL080 should be between these two

areas. Furthermore, all components in the reference circuitry

and the input signal chain that are connected to ground

should be connected together with short traces and enter the

ground plane at a single, quiet point. All ground connections

should have a low inductance path to ground.

6.0 DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source

driving the CLK input must be free of jitter. Isolate the ADC

clock from any digital circuitry with buffers, as with the clock

tree shown in Figure 7. The gates used in the clock tree must

be capable of operating at frequencies much higher than

those used if added jitter is to be prevented.

Best performance will be obtained with a differential input

drive, compared with a single-ended drive, as discussed in

Sections 1.3.1 and 1.3.2.

As mentioned in Section 5.0, it is good practice to keep the

ADC clock line as short as possible and to keep it well away

from any other signals. Other signals can introduce jitter into

the clock signal, which can lead to reduced SNR perfor-

mance, and the clock can introduce noise into other lines.

Even lines with 90˚ crossings have capacitive coupling, so

try to avoid even these 90˚ crossings of the clock line.

7.0 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, all inputs should not go

more than 100 mV beyond the supply rails (more than

100 mV below the ground pins or 100 mV above the supply

pins). Exceeding these limits on even a transient basis may

cause faulty or erratic operation. It is not uncommon for high

speed digital components (e.g., 74F and 74AC devices) to

exhibit overshoot or undershoot that goes above the power

supply or below ground. A resistor of about 47

Ω to 100Ω in

series with any offending digital input, close to the signal

source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage,

even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12DL080

with a device that is powered from supplies outside the

range of the ADC12DL080 supply. Such practice may lead to

conversion inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus.

The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current

flows through V

DR and DR GND. These large charging cur-

rent spikes can couple into the analog circuitry, degrading

dynamic performance. Adequate bypassing and maintaining

separate analog and digital areas on the pc board will reduce

this problem. Additionally, bus capacitance beyond the

specified 10 pF/pin will cause t

OD to increase, making it

difficult to properly latch the ADC output data. The result

could, again, be an apparent reduction in dynamic perfor-

mance.

The digital data outputs should be buffered (with 74ACQ541,

for example). Dynamic performance can also be improved

by adding series resistors at each digital output, close to the

ADC12DL080, which reduces the energy coupled back into

the converter output pins by limiting the output current. A

reasonable value for these resistors is 100

Ω.

Using an inadequate amplifier to drive the analog input.

As explained in Section 1.3, the capacitance seen at the

input alternates between 8 pF and 7 pF, depending upon the

phase of the clock. This dynamic load is more difficult to

drive than is a fixed capacitance. If the amplifier exhibits

overshoot, ringing, or any evidence of instability, even at a

very low level, it will degrade performance. A small series

resistor at each amplifier output and a capacitor at the

analog inputs (as shown in Figure 5) will improve perfor-

mance.

Also, it is important that the signals at the two inputs have

exactly the same amplitude and be exactly 180o out of phase

with each other. Board layout, especially equality of the

length of the two traces to the input pins, will affect the

effective phase between these two signals. Remember that

an operational amplifier operated in the non-inverting con-

figuration will exhibit more time delay than will the same

device operating in the inverting configuration.

Operating with the reference pins outside of the speci-

fied range. As mentioned in Section 1.2, V

REF should be in

the range of

0.8V

≤ V

REF

≤ 1.2V

Operating outside of these limits could lead to performance

degradation.

Inadequate network on Reference Bypass pins (V

RPA,

RNA, VRMA, VRPB, VRNB and VRMB). As mentioned in

Section 1.2, these pins should be bypassed with 0.1 µF

capacitors to ground at V

RMA and VRMB and with a 10 µF

between pins V

RPA and VRNA and between VRPB and VRNB

for best performance.

Using a clock source with excessive jitter, using exces-

sively long clock signal trace, or having other signals

coupled to the clock signal trace. This will cause the

sampling interval to vary, causing excessive output noise

and a reduction in SNR and SINAD performance.

20169417

FIGURE 7. Isolating the ADC Clock from other Circuitry

with a Clock Tree

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