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DS20005721C-page 7

HV2803/HV2903/HV2904

TABLE 1-1:

TRUTH TABLE(1,2,3,4,5,6)

STBY MODE D0 D1 ... D15 D16 ... D31 DIN/AB LE/EN CLR SW0 SW1 ... SW15 SW16 ... SW31

HH

L

—

...

——

...

—X

L

L

OFF

—

...

——

...

—

HH

H —

—

—

—

X

L

L

ON

—

—

—

—

HH

—

L

—

—

—

X

L

L

—

OFF

—

—

—

HH

— H

—

—

—

X

L

L

—

ON

—

—

—

HH

— —

—

—

—

X

L

L

—

—

—

—

—

HH

— —

—

—

—

X

L

L

—

—

—

—

—

HH

— —

L

—

—

X

L

L

—

—

OFF

—

—

HH

— —

H

—

—

X

L

L

—

—

ON

—

—

HH

— —

—

L

—

X

L

L

—

—

—

OFF

—

HH

— —

—

H

—

X

L

L

—

—

—

ON

—

HH

— —

—

—

—

X

L

L

—

—

—

—

—

HH

— —

—

—

—

X

L

L

—

—

—

—

—

HH

— —

—

—

L

X

L

L

—

—

—

—

OFF

HH

— —

—

—

H

X

L

L

—

—

—

—

ON

H

H

X

X

X

X

X

X

X

X

H

L

HOLD PREVIOUS STATE

H

H

X

X

X

X

X

X

X

X

X

H

ALL SWITCHES OFF

H

L

X

X

X

X

X

X

X

L

H

X

EVEN SWITCHES OFF & ODD SWITCHES ON

H

L

X

X

X

X

X

X

X

H

H

X

EVEN SWITCHES ON & ODD SWITCHES OFF

H

L

X

X

X

X

X

X

X

X

L

X

ALL SWITCHES OFF

L

X

X

X

X

X

X

X

X

X

X

X

ALL SWITCHES OFF, STANBY STATE

Legend: X = Don’t care; L = Low; H = High.

Note 1: The 32 switches operate independently (when MODE = H).

2: Serial data are clocked in on the L to H transition of the CLK (when MODE = H).

3: All 32 switches go to a state retaining their latched condition at the rising edge of LE/EN. When LE/EN is

low, the shift registers’ data flow through the latch (when MODE = H).

4: DOUT is high when data in Register 31 are high (when MODE = H).

5: Shift register clocking has no effect on the switch states if LE/EN is high (when MODE = H).

6: The CLR (clear) input overrides all the inputs (when MODE = H).