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AX88772 Datasheet(PDF) 36 Page - ASIX Electronics Corporation |
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AX88772 Datasheet(HTML) 36 Page - ASIX Electronics Corporation |
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36 / 42 page ![]() AX88772 USB to 10/100 Fast Ethernet/HomePNA Controller 8.4.1.2 XIN25M TP_XIN25M TH_XIN25M TL_XIN25M TR_XIN25M TF_XIN25M VIH VIL Symbol Parameter Condition Min Typ Max Unit TP_XIN25M XIN25M clock cycle time - 40.0 - ns TH_XIN25M XIN25M clock high time - 20.0 - ns TL_XIN25M XIN25M clock low time - 20.0 - ns TR_XIN25M XIN25M rise time VIL (max) to VIH (min) - - 1.0 ns TF_XIN25M XIN25M fall time VIH (min) to VIL (max) - - 1.0 ns 8.4.2 Reset Timing XIN12M RESET_N Symbol Description Min Typ Max Units Trst Reset pulse width (6ms ~10ms) after XIN12M is running 72000 - - XIN12M clock cycle 8.4.3 MII Timing (100Mbps) Ttclk Ttch Ttcl TX_CLK Tts Tth TXD [3:0] TX_EN, TX_ER Trst Symbol Description Min Typ Max Units Ttclk TX_CLK clock cycle time *1 - 40.0 - ns Ttch TX_CLK clock high time *2 - 20.0 - ns Ttcl TX_CLK clock low time *2 - 20.0 - ns Tts TXD [3:0], TX_EN, TX_ER setup time 28.0 - - ns Tth TXD [3:0], TX_EN, TX_ER hold time 5.0 - - ns ASIX ELECTRONICS CORPORATION 36 |
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