MPC8610EC datasheet(28/96 Pages) NXP

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor

Table 20 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.

Table 21 provides the input AC timing specifications for the DDR SDRAM interface.

Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).

Figure 4. DDR Input Timing Diagram for tDISKEW

Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.31

AC input high voltage

VIH

MVREF + 0.31

—

Table 21. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

tCISKEW

1, 2

533 MHz

400 MHz

333 MHz

–300

–365

–390

300

365

390

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[

n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

3. Maximum DDR1 frequency is 400 MHz.

MCK[

tMCK

MDQ[x]

MDQS[

tDISKEW

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