74HC173N datasheet(10/10 Pages) PHILIPS

10 / 10 page

December 1990

Philips Semiconductors

Product speciﬁcation

Quad D-type ﬂip-ﬂop; positive-edge trigger;

3-state

74HC/HCT173

AC WAVEFORMS

Fig.6

Waveforms showing the clock (CP) to

output (Qn) propagation delays, the clock

pulse width, the output transition times and

the maximum clock pulse frequency.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7

Waveforms showing the master reset (MR)

pulse width, the master reset to output (Qn)

propagation delays and the master reset to

clock (CP) removal time.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the 3-state enable and

disable times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”.

Fig.9 Waveforms showing the data set-up and hold

times from input (En, Dn) to clock (CP).

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

74HC173N Datasheet(PDF) 10 Page - NXP Semiconductors