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AM69AX Datasheet(PDF) 145 Page - Texas Instruments

Part # AM69AX
Description  AM69Ax Processors, Silicon Revision 1.0
PDF  299 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM69AX Datasheet(HTML) 145 Page - Texas Instruments

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Note
The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1,
February 17, 2014.
Note
The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v
1.4 February 23, 2016.
Note
The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort
(eDP) Standard v1.4b October 23, 2015.
7.6.13 DDR0 Electrical Characteristics
Note
The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.
7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only
for High-Security Devices.
7.7.1 Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
See Recommended Operating Conditions
V
VDD_MCU
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
See Recommended Operating Conditions
V
VPP_CORE
Supply voltage range for the eFuse ROM
domain during normal operation
N/A(2)
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.71
1.8
1.89
V
VPP_MCU
Supply voltage range for the eFuse ROM
domain during normal operation
N/A(2)
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.71
1.8
1.89
V
(1)
Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70018-Q1 from the TLV707x
family meet the supply voltage range needed for VPP_CORE and VPP_MCU.
(2)
N/A stands for Not Applicable.
7.7.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.
• The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up
sequence (for more details, see Power Supply Sequencing).
7.7.3 Programming Sequence
Programming sequence for OTP eFuses:
www.ti.com
AM69A
SPRSP92 – FEBRUARY 2023
Copyright © 2023 Texas Instruments Incorporated
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145
Product Folder Links: AM69A



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