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AM69AX Datasheet(PDF) 189 Page - Texas Instruments |
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AM69AX Datasheet(HTML) 189 Page - Texas Instruments |
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189 / 299 page  7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode see Figure 7-39 NO. MODE MIN MAX UNIT RGMII1 tc(rxc) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(rxcH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(rxcL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode see Figure 7-39 NO. MODE MIN MAX UNIT RGMII4 tsu(rdV-rxcV) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(rx_ctlV-rxcV) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(rxcV-rdV) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(rxcV-rx_ctlV) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3 _ [ :0] (B) RGMII[x] RX_CTL _ (B) RGMII[x] RXC _ (A) RGMII4 RXERR RXDV 2nd Half-byte 1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 7-39. CPSW2G Receive Interface Timing, RGMII Operation Section 7.10.5.2.3.3, Section 7.10.5.2.3.4 present switching characteristics for transmit - RGMII for 10 Mbps, 100 Mbps, and 1000 Mbps. www.ti.com AM69A SPRSP92 – FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: AM69A |
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