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Table 7-34. DPI External Pixel Clock Timing Requirements

NO.(2)

MIN

MAX

UNIT

tc(extpclkin)

Cycle time, VOUT(x)_EXTPCLKIN

6.06

tw(extpclkinL)

Pulse duration, VOUT(x)_EXTPCLKIN low

0.45×P

(1)

tw(extpclkinH)

Pulse duration, VOUT(x)_EXTPCLKIN high

0.45×P

(1)

P = output VOUT(x)_PCLK period in ns.

(2)

x in VOUT(x) = 1 or 2

VOUT(x)_EXTPCLKIN

DPI_TIMING_02

Falling-edge Clock Reference

Rising-edge Clock Reference

VOUT(x)_EXTPCLKIN

Figure 7-43. DPI External Pixel Clock Input

For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device

TRM.

7.10.5.6 eCAP

The supported features by the device ECAP are:

• 32-bit time base counter

• 4-event time-stamp registers (each 32 bits)

• Independent edge polarity selection for up to four sequenced time-stamp capture events

• Interrupt capabilities on any of the four capture events

• Input capture signal pre-scaling (from 1 to 16)

• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp

capture or difference mode time-stamp capture)

Table 7-35 represents ECAP timing conditions.

Table 7-35. ECAP Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

Section 7.10.5.6.1 and Section 7.10.5.6.2 present timing and switching characteristics for eCAP (see Figure 7-44

and Figure 7-45).

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AM69A

SPRSP92 – FEBRUARY 2023

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