AM69AX datasheet(267/299 Pages) TI

267 / 299 page

8 Detailed Description

8.1 Overview

The AM69A processor family is based on the evolutionary Jacinto 7 architecture, targeted at ADAS and

Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade

of TI’s leadership in the ADAS processor market. The AM69A provides high performance compute for both

traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system

integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor

modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and

vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors

for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and

isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Note

For more information on features, subsystems, and architecture of superset device System on Chip

(SoC), see the device TRM.

8.2 Functional Block Diagram

Figure 8-1 is functional block diagram for the device.

www.ti.com

AM69A

SPRSP92 – FEBRUARY 2023

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AM69AX Datasheet(PDF) 267 Page - Texas Instruments