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8.5 Other Subsystems

8.5.1 MSMC

The

Multicore

Shared

Memory

Controller

(MSMC)

forms

the

heart

the

compute

cluster

(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected

processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute

cluster.

For more information, see Multicore Shared Memory Controller (MSMC) section in Device Configuration chapter

in the device TRM.

8.5.2 NAVSS

8.5.2.1 NAVSS0

Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and

Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), Virtualization translation (VirtSS), and

a North Bridge (NBSS).

8.5.2.2 MCU_NAVSS

MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated

in the MCU domain.

MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator

(UDMASS), and Peripherals (Module subsystem [MODSS]).

For more information, see Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem (MCU NAVSS)

sections in the device TRM.

8.5.3 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer

needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard

non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which

require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and

supporting only statically configured Transfer Request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the peripherals

themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data

stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of

the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to

a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.

The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer

complexity at each point in the system to match the requirements of whatever is being transferred to or

from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO

dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically

for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.

Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous

transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and

employs round-robin scheduling between channels in order to share the underlying DMA hardware.

For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.

8.5.4 Power Supply

The device requires 6 power supply types and 1 internal LDO connection type, see Power Supply Signal

Descriptions

• Digital IO Voltages

• Digital Low Voltages

• Digital AVS Voltage

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AM69A

SPRSP92 – FEBRUARY 2023

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