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8.5.5.14 eQEP

The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary

incremental encoder to get position, direction and speed information from a rotating machine for use in high

performance motion and position control system. The disk of an incremental encoder is patterned with a single

track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is

defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second

track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used

to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as

index, marker, home position and zero reference.

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter

in the device TRM.

8.5.5.15 GPIO

The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, the user can write to an internal register to

control the state driven on the output pin. When configured as an input, user can obtain the state of the input by

reading the state of an internal register.

In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different

interrupt/event generation modes.

For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

8.5.5.16 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external

memory devices like:

• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

• NAND flash

• Pseudo-SRAM devices

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

8.5.5.17 Hyperbus

The Hyperbus module is a part of the device Flash Subsystem (FSS).

The Hyperbus module is low pin count memory interface that provides high read/write performance. The

Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol

for read and write transactions.

There is one Hyperbus™ module inside the device. The Hyperbus module includes one Hyperbus Memory

Controller (HBMC).

For more information, see Hyperbus Interface section in Peripherals chapter in the device TRM.

8.5.5.18 I2C

The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface

between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I2C-bus-compatible

device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit

and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.

Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.

The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and

support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1,

I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate

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AM69A

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