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The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 11-4 limits the input

current to the actual device pin in a case where VBUS is applied while the device is powered off.

11.4 System Power Supply Monitor Design Guidelines using VMON/POK

The VMON1_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is

typically a single pre-regulated power source for the entire system. This supply is monitored by comparing

the output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with

a power fail event being triggered when the voltage applied to VMON1_ER_VSYS drops below the internal

reference voltage. The actual system power supply voltage trip point is determined by the system designer when

selecting component values used to implement the external resistor voltage divider circuit. When designing the

resistor divider circuit it is important to understand various factors which contribute to variability in the system

power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON1_ER_VSYS input

threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar

thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability

contributed by resistor value tolerances. Input leakage current associated with VMON1_ER_VSYS must also

be considered since any current flowing into the pin creates a loading error on the voltage divider output. The

VMON1_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V.

Note

The resistor voltage divider shall be designed such that its output voltage never exceeds the

maximum value defined in Section 7.4 during normal operating conditions.

Figure 11-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger

threshold is 5 V - 10%, or 4.5 V.

For this example, it is important to understand which variables effect the maximum trigger threshold when

selecting resistor values. It is obvious a device which has a VMON1_ER_VSYS input threshold of 0.45 V + 3%

needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops

10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions

effect the maximum trigger point may not be obvious. When selecting component values which produce a

maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and

the value of R2 is 1% high combined with a condition where input leakage current for the VMON1_ER_VSYS pin

is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum

trigger threshold of 4.523 V.

Once component values have been selected to satisfy the maximum trigger voltage as described above, the

system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an

output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input

leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result

is a minimum trigger threshold of 4.008 V.

This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.

Approximately 250 mV of this range is introduced by VMON1_ER_VSYS input threshold accuracy of ±3%,

approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this

range is introduced by loading error when VMON1_ER_VSYS input leakage current is 2.5 μA.

The resistor values selected in this example produces approximately 100 μA of bias current through the resistor

divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to

about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor

divider bias current vs loading error is something the system designer needs to consider when selecting

component values.

The system designer should also consider implementing a noise filter on the voltage divider output since

VMON1_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done

by installing a capacitor across R1 as shown in Figure 11-5. However, the system designer must determine the

response time of this filter based on system supply noise and expected response to transient events.

AM69A

SPRSP92 – FEBRUARY 2023

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