M95640-DF datasheet(31/53 Pages) STMICROELECTRONICS

Part #	M95640-DF

Description	64-Kbit serial SPI bus EEPROM with high-speed clock

PDF	53 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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31 / 53 page

DocID16877 Rev 19

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M95640-W M95640-R M95640-DF

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

•

Standby power mode,

•

deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started),

•

not in the Hold condition,

•

the Write Enable Latch (WEL) is reset to 0,

•

Write In Progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous

power-down (they are non-volatile bits).

7.2

Initial delivery state

The device is delivered with the memory array bits and identification page bits set to all 1s

(each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and

BP0) bits are initialized to 0.

M95640-DF Datasheet(PDF) 31 Page - STMicroelectronics