SW52212 datasheet(15/71 Pages) SILABS

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Parameter

Symbol

Condition

Min

Typ

Max

Unit

LVCMOS – REF (VDD = 1.8 V ±5%)

Long Accuracy

ppm

Variation from reference

frequency

ppm

Clock Period

TPERIOD

25 MHz output

—

Slew Rate

Trf

Byte 2[1:0] = 48 (Slowest), 20% to

80% of VDDREF

—

0.7

1.3

V/ns

Byte 2[1:0] = 49 (Slow), 20% to

80% of VDDREF

—

1.0

1.6

V/ns

Byte 2[1:0] = 4A (Fast), 20% to

80% of VDDREF

—

1.1

1.9

V/ns

Byte 2[1:0] = 4B (Fastest), 20% to

80% of VDDREF

—

1.2

2.0

V/ns

Duty Cycle1

TDC_REF

VT = VDD/2 V

Cycle-to-Cycle Jitter

TCCJ_REF

VT = VDD/2 V using "SLOW" Set-

ting

—

Phase Jitter

RMSREF

12 kHz to 5 MHz

—

0.3

0.4

REF Noise Floor

TJ1kHz_REF

1 kHz offset

—

–132

–124

dBc

REF Noise Floor

TJ10kHz_REF

10 kHz offset to Nyquist

—

–145

–139

dBc

DIFF HCSL

Duty Cycle

TDC

Measured at 0 V differential

Output-to-Output Skew

TSKEW

Measured at 0 V differential

—

Slew Rate

TR/TF

Measured differentially from

±150 mV (fast setting)

—

2.4

3.7

V/ns

Measured differentially from

±150 mV (slow setting)

—

1.9

2.9

V/ns

Slew Rate Matching

Delta TR/TF

—

Max modulation frequency

df/dt

Tmax-freqmod-

slew

—

1250

ppm/usec

Voltage High

VHIGH

600

—

850

Voltage Low

VLOW

–150

—

150

Max Voltage

VMAX

—

750

1150

Min Voltage

VMIN

–300

—

Crossing Point Voltage

VOX

Absolute crossing point voltage at

0.7 V Swing

250

—

550

Crossing Point Voltage (var)

VOX_DELTA

Variation of VOX over all rising

clock edges

—

Modulation Frequency

FMOD

31.5

kHz

Enable/Disable and Setup

Clock Stabilization from

Power-up

TSTABLE

Min ramp rate 200V/s

—

Data Sheet

Electrical Specifications

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