HC705JJ7GRSSLASHD datasheet(183/230 Pages) NXP

183 / 230 page

EPROM/OTPROM

EPROM Registers

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

EPROM/OTPROM

SWAIT — STOP Conversion to WAIT

This EPROM bit disables the STOP instruction and prevents

inadvertently turning off the COP watchdog with a STOP instruction.

When the SWAIT bit is set, a STOP instruction puts the MCU in halt

mode. Halt mode is a wait-like low-power state. The internal oscillator

and timer clock continue to run, but the CPU clock stops. When the

SWAIT bit is clear, a STOP instruction stops the internal oscillator, the

internal clock, the CPU clock, the timer clock, and the COP watchdog

timer.

1 = STOP instruction converted to WAIT instruction

0 = STOP instruction not converted to WAIT instruction

LVREN — Low-Voltage Reset Enable

This EPROM bit enables the low-voltage reset (LVR) function.

1 = LVR function enabled

0 = LVR function disabled

PIRQ — Port A IRQ Enable

This EPROM bit enables the PA3–PA0 pins to function as external

interrupt sources.

1 = PA3–PA0 enabled as external interrupt sources

0 = PA3–PA0 not enabled as external interrupt sources

LEVEL — External Interrupt Sensitivity

This EPROM bit makes the external interrupt inputs level-triggered as

well as edge-triggered

1 = IRQ/VPP pin negative-edge triggered and low-level triggered;

PA3–PA0 pins positive-edge triggered and high-level triggered

0 = IRQ/VPP pin negative-edge triggered only; PA3–PA0 pins

positive-edge triggered only

COPEN — COP Watchdog Enable

This EPROM bit enables the COP watchdog.

1 = COP watchdog enabled

0 = COP watchdog disabled

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 183 Page - NXP Semiconductors