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HC705RC17GRS/D Datasheet(PDF) 23 Page - NXP Semiconductors |
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HC705RC17GRS/D Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 126 page  General Description Signal Description MC68HC705RC17 — Rev. 2.0 General Release Specification General Description 1.5.10 XFC This pin provides a means for connecting an external filter capacitor to the synthesizer phase-locked loop filter. (For additional information concerning this capacitor, refer to Section 10. Phase-Locked Loop (PLL) Synthesizer.) 1.5.11 VDDSYN This pin provides a separate power connection to the PLL synthesizer which should be at the same potential as VDD. NOTE: Any unused inputs, I/O ports, and no connects should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC705RC17 do not require termination, termination is recommended to reduce the possibility of static damage. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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