HC805P18GRSSLASHD datasheet(49/111 Pages) NXP

49 / 111 page

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

Rev. 1.0

7.6 I/O Port Programming

Each pin on ports A through port D (except pin 7 of port D) may be programmed

as an input or an output under software control as shown in Table 7-1, Table 7-2,

Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its

corresponding bit in the associated port data direction register (DDR). A pin is

configured as an output if its corresponding DDR bit is set to a logic one. A pin is

configured as an input if its corresponding DDR bit is cleared to a logic zero.

Table 7-1. Port A I/O Functions

DDRA

I/O Pin Mode

Access to DDRA

@ $0004

Access to Data

Read/Write

Read

Write

Input, High Impedance

DDRA0–DDRA7

I/O Pin

Output

DDRA0–DDRA7

PA0–PA7

*Does not affect input, but stored to data register

Table 7-2. Port B I/O Functions

DDRB

I/O Pin Mode

Access to DDRA

@ $0005

Access to Data

Read/Write

Read

Write

Input, High Impedance

DDRB5–DDRB7

I/O Pin

Output

DDRB5–DDRB7

PB5–PB7

*Does not affect input, but stored to data register

Table 7-3. Port C I/O Functions

DDRA

I/O Pin Mode

Access to DDRA

@ $0006

Accesses to Data

Read/Write

Read

Write

Input, High Impedance

DDRC0–DDRC7

I/O Pin

Output

DDRC0–DDRC7

PC0–PC7

*Does not affect input, but stored to data register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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