AD5744CSU datasheet(7/27 Pages) AD

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Preliminary Technical Data

Rev. PrA 15-Nov-04| Page 7 of 27

TIMING CHARACTERISTICS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;

DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter7,8,9

Limit at TMIN, TMAX

Unit

Description

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

t5 10

ns min

24th SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

Data setup time

ns min

Data hold time

ns min

SYNC rising edge to LDAC falling edge

t10

ns min

LDAC pulse width low

t11

ns min

LDAC falling edge to DAC output response time

t12

µs max

DAC output settling time

t13

ns min

CLR pulse width low

t14

µs max

CLR pulse activation time

t1511,12

ns max

SCLK rising edge to SDO valid

t1612

ns min

SCLK falling edge to SYNC rising edge

t1712

ns min

SYNC rising edge to LDAC falling edge

7 Guaranteed by design and characterization. Not production tested.

8 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

9 See Figure 2, Figure 3, and Figure 4.

10 Stand-alone mode only.

11 Measured with the load circuit of Figure 5.

12 Daisy-chain mode only.

AD5744/AD5764

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