AD5744CSU datasheet(24/27 Pages) AD

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Preliminary Technical Data

Rev. PrA 15-Nov-04| Page 24 of 27

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful

consideration of the power supply and ground return layout

helps to ensure the rated performance. The printed circuit

board on which the AD5744/64 is mounted should be designed

so that the analog and digital sections are separated and

confined to certain areas of the board. If the AD5744/64 is in a

system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

The AD5744/64 should have ample supply bypassing of 10 µF

parallel with 0.1 µF on each supply located as close to the

package as possible, ideally right up against the device. The 10

µF capacitors are the tantalum bead type. The 0.1 µF capacitor

should have low effective series resistance (ESR) and low

effective series inductance (ESI) such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

The power supply lines of the AD5744/64 should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digital ground to

avoid radiating noise to other parts of the board, and should

never be run near the reference inputs. A ground line routed

between the SDIN and SCLK lines helps reduce crosstalk

between them (not required on a multilayer board, which has a

separate ground plane, but separating the lines helps). It is

essential to minimize noise on the reference inputs, because it

couples through to the DAC output.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feed through the board. A

microstrip technique is by far the best, but not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground plane, while signal

traces are placed on the solder side.

ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled. Opto-isolators can provide voltage isolation in

excess of 3 kV. The serial loading structure of the AD5744/64

makes it ideal for opto-isolated interfaces, because the number

of interface lines is kept to a minimum. Figure 12 shows a 4-

channel isolated interface to the AD5744/64. To reduce the

number of opto-isolators, if the simultaneous updating of the

DAC is not required, the LDAC pin may be tied permanently

low. The DAC can then be updated on the rising edge of SYNC.

DVCC

TO SDIN

TO SCLK

TO SYNC

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

µCONTROLLER

OPTO-COUPLER

TO LDAC

CONTROL OUT

Figure 12. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5744/64 is via a serial bus

that uses standard protocol compatible with microcontrollers

and DSP processors. The communications channel is a 3-wire

(minimum) interface consisting of a clock signal, a data signal,

and a synchronization signal. The AD5744/64 requires a 24-bit

data word with data valid on the falling edge of SCLK.

For all the interfaces, the DAC output update may be done

automatically when all the data is clocked in, or it may be done

under the control of LDAC. The contents of the DAC register

may be read using the readback function.

AD5744/64 to MC68HC11 Interface

Figure 13 shows an example of a serial interface between the

AD5744/64 and the MC68HC11 microcontroller. The serial

peripheral interface (SPI) on the MC68HC11 is configured for

master mode (MSTR = 1), clock polarity bit (CPOL = 0), and

the clock phase bit (CPHA = 1). The SPI is configured by

writing to the SPI control register (SPCR)-----see the 68HC11

User Manual. SCK of the 68HC11 drives the SCLK of the

AD5744/64, the MOSI output drives the serial data line (DIN)

the AD5744/64, and the MISO input is driven from SDO. The

SYNC is driven from one of the port lines, in this case PC7.

When data is being transmitted to the AD5744/64, the SYNC

line

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