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STM32U5A5QJI Datasheet(PDF) 64 Page - STMicroelectronics |
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STM32U5A5QJI Datasheet(HTML) 64 Page - STMicroelectronics |
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64 / 382 page  Functional overview STM32U5Axxx 64/382 DS13543 Rev 1 a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may require the application to re-configure and recenter the output clock phase with the received data. The delay block main features are: • Input clock frequency ranging from 25 to 160 MHz • Up to 12 oversampling phases 3.30 Hexadeca-SPI interface (HSPI) The HSPI supports most external serial memories such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAMs and HyperFlash memories, with the following functional modes: • Indirect mode: all the operations are performed using the HSPI registers. • Status polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting. • Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation. The HSPI supports the following protocols with associated frame formats: • the standard frame format with the command, address, alternate byte, dummy cycles and data phase • the HyperBus frame format The HSPI offers the following features: • Three functional modes: Indirect, Status-polling, and Memory-mapped • Read and write support in Memory-mapped mode • Support for single, dual, quad, octal and hexadeca communication • Dual-quad mode, where eight bits can be sent/received simultaneously by accessing two quad or two octal memories in parallel • SDR (single-data rate) and DTR (double-transfer rate) support • Data strobe support • Fully programmable opcode • Fully programmable frame format • Support wrapped-type access to memory in read direction • HyperBus support • Integrated FIFO for reception and transmission • 8-, 16-, and 32-bit data accesses allowed • DMA channel for Indirect mode operations • Interrupt generation on FIFO threshold, timeout, operation complete, and access error • High-speed interface up to 160MHz 3.30.1 HSPI TrustZone security When the TrustZone security is enabled, the whole HSPI bank is secure after reset. Up to two nonsecure areas can be configured thought the TZSC MPCWM6 controller with a granularity of 64 Kbytes. |
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