STM32G0C1NET3 datasheet(34/159 Pages) STMICROELECTRONICS

34 / 159 page

Functional overview

STM32G0C1xC/xE

34/159

DS13564 Rev 4

They provide hardware management of the CTS, RTS and RS485 DE signals,

multiprocessor communication mode, master synchronous communication and single-wire

half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have

a clock domain independent of the CPU clock, which allows them to wake up the MCU from

Stop mode. The wakeup events from Stop mode are programmable and can be:

•

start bit detection

•

any received data frame

•

a specific programmed data frame

All USART interfaces can be served by the DMA controller.

3.24

Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds two LPUARTs. The peripheral supports asynchronous serial

communication with minimum power consumption. It supports half duplex single wire

communication and modem operations (CTS/RTS). It allows multiprocessor

communication.

The LPUART has a clock domain independent of the CPU clock, and can wakeup the

system from Stop mode. The Stop mode wakeup events are programmable and can be:

•

start bit detection

•

any received data frame

•

a specific programmed data frame

Table 9. USART implementation

USART modes/features(1)

1. X: supported

USART1

USART2

USART3

USART4

USART5

USART6

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

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