6.42

71V321L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

10

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled

by Address Match Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. IftAPSisnotsatisfied,theBUSYwillbeassertedononesideortheother,butthereisnoguaranteeonwhichsideBUSYwillbeasserted.

NOTES:

1. tWHmustbemetfor BUSYoutput71V321.

2. BUSYisassertedonport'B'blockingR/W'B',untilBUSY'B'goesHIGH.

3. Alltimingisthesamefortheleftandrightports.Port"A"maybeeithertheleftorrightport.Port"B"isoppositefromport"A".

Timing Waveform of Write with BUSY(3)

BUSY"B"

3026 drw 11

R/

W"A"

tWP

tWH

R/

W"B"

(2)

(1)

,

tAPS

(2)

ADDR

"A" AND "B"

ADDRESSES MATCH

tBAC

tBDC

CE"B"

CE"A"

BUSY"A"

3026 drw 12

BUSY"B"

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

tAPS

ADDR"A"

ADDR"B"

tRC OR tWC

3026 drw 13

(2)

tBAA

tBDA