6.42

71V321L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

13

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesabusyindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYLogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation.

Depth Expansion

The BUSY arbitration, is based on the chip enable and address

signals only. It ignores whether an access is a read or write.

TheBUSYoutputsontheIDT71V321aretotem-poletypeoutputsand

do not require pull-up resistors to operate. If these RAMs are being

expanded in depth, then the BUSY indication for the resulting array

requires the use of an external AND gate

Functional Description

The IDT7V1321 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT71V321 has an automatic power down

feature controlled by CE. TheCEcontrolson-chippowerdowncircuitry

that permits the respective port to go into a standby mode when not

selected(CE=VIH).Whenaportisenabled,accesstotheentirememory

arrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 7FE

(HEX), whereawriteisdefinedastheCER =R/WR=VILperTruthTable

II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen

CEL = OEL = VIL,R/W is a "don't care". Likewise, the right port interrupt

flag (INTR) is asserted when the left port writes to memory location 7FF

(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe

memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,

sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

3026 drw 16

BUSYR

MASTER

Dual Port

RAM

BUSYL

BUSYR

CE

MASTER

Dual Port

RAM

BUSYL

BUSYR

CE

BUSYL

Figure3.Busyandchipenableroutingfor depth

expansionwithIDT71V321.