83C752 datasheet(18/24 Pages) PHILIPS

18 / 24 page

Philips Semiconductors

Product specification

83C752/87C752

80C51 8-bit microcontroller family

2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01

EPROM PROGRAMMING AND VERIFICATION

Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V

SYMBOL

PARAMETER

MIN

MAX

UNIT

1/tCLCL

Oscillator/clock frequency

1.2

MHz

tAVGL1

Address setup to P0.1 (PROG–) low

µs + 24tCLCL

tGHAX

Address hold after P0.1 (PROG–) high

48tCLCL

tDVGL

Data setup to P0.1 (PROG–) low

38tCLCL

tDVGL

Data setup to P0.1 (PROG–) low

38tCLCL

tGHDX

Data hold after P0.1 (PROG–) high

36tCLCL

tSHGL

VPP setup to P0.1 (PROG–) low

µs

tGHSL

VPP hold after P0.1 (PROG–)

µs

tGLGH

P0.1 (PROG–) width

110

µs

tAVQV2

VPP low (VCC) to data valid

48tCLCL

tGHGL

P0.1 (PROG–) high to P0.1 (PROG–) low

µs

tSYNL

P0.0 (sync pulse) low

4tCLCL

tSYNH

P0.0 (sync pulse) high

8tCLCL

tMASEL

ASEL high time

13tCLCL

tMAHLD

Address hold time

2tCLCL

tHASET

Address setup to ASEL

13tCLCL

tADSTA

Low address to address stable

13tCLCL

NOTES:

1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP).

2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.

A0–A10

ADDRESS STROBE

PROGRAMMING

PULSES

VPP/VIH VOLTAGE

SOURCE

CLK SOURCE

RESET

CONTROL

LOGIC

87C752

P3.0–P3.7

P0.0/ASEL

P0.1

P0.2

XTAL1

RESET

VCC

VSS

P1.0–P1.7

+5V

DATA BUS

SU00320

Figure 7. Programming Configuration

MIN 2 MACHINE

CYCLES

TEN BIT SERIAL CODE

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

UNDEFINED

XTAL1

RESET

P0.2

P0.1

SU00302

Figure 8. Entry into Program/Verify Modes

83C752 Datasheet(PDF) 18 Page - NXP Semiconductors

83C752 Datasheet(HTML) 18 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL