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DA16200 Datasheet(PDF) 117 Page - Renesas Technology Corp |
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DA16200 Datasheet(HTML) 117 Page - Renesas Technology Corp |
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117 / 154 page ![]() DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 117 of 153 © 2023 Renesas Electronics Table 174: HIF_AHB_SA (0x5003_0050) Bit Mode Symbol Description Reset 31:0 R HIF_AHB_SA This register specifies the start address of AHB bus for data transfer 32'h00 Table 175: HIF_AHB_EA (0x5003_0054) Bit Mode Symbol Description Reset 31:0 R HIF_AHB_EA This register specifies the end address of AHB bus for data transfer 32'h00 Table 176: HIF_BUS_ST (0x5003_0060) Bit Mode Symbol Description Reset 31:8 - - Reserved 7 R/W RSP_RET_ST Receive the response from the device 0: Not receive 1: Receive 1'b0 6 R CMD_BUSY CMD/RSP Status Machine Busy Status 0: Not ongoing command/response (Idle) 1: Have ongoing command/response (Busy) 1'b0 5 R DAT_BUSY Data Status Machine Busy Status 0: Not ongoing data transfer (Idle) 1: Have ongoing data transfer (Busy) 1'b0 4 R HCMD_ST Status of Host Interface CMD signal 1'b0 3:0 R RSP_CMD_IDX Status of Host Interface Data signals 4'h0 Table 177: HIF_SM_ST (0x5003_0064) Bit Mode Symbol Description Reset 31:16 R HIF_DAT_CNT Data Count Status 16'h0 15:13 - - Reserved 12:8 R HIF_DAT_SM Data State Machine Status 5'h0 7:5 - - Reserved 4:0 R HIF_CMD_SM CMD/RSP State Machine Status 5'h0 Table 178: HIF_XTR_CNT (0x5003_0068) Bit Mode Symbol Description Reset 31:24 - - Reserved 23:0 R RSP_TMO_CNT Transferred Data Block Count Status This register reports the number of the transferred data blocks. The value of this counter will be cleared after a new read/write command has been sent 24'h00 |
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