FN9309 Rev.3.00

Page 21 of 34

Jul 8, 2019

RAA212421

4. Functional Description

Over-temperature faults also force PG1 low until the fault condition is cleared by an attempt to soft-start. PG1 has

an internal 5MΩ pull-up resistor.

4.4

PWM Control Scheme (Buck)

The wide VIN buck regulator employs peak current-mode Pulse-Width Modulation (PWM) control for fast transient

response and pulse-by-pulse current limiting as shown in the “Functional Block Diagram” on page 4. The current loop

consists of the current sensing circuit, slope compensation ramp, PWM comparator, oscillator, and latch. Current sense

trans-resistance is typically 500mV/A and the slope compensation rate, Se, is typically 450mV/T where T is the switching

cycle period. The control reference for the current loop comes from the error amplifier’s output (VCOMP1).

A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET is turned on. Current begins to ramp up in

the upper FET and inductor. This current is sensed, converted to a voltage (VCSA), and summed with the slope compensation

signal. This combined signal is compared to VCOMP1, and the latch is reset when the signal is equal to VCOMP1. Upon latch

reset, the upper FET is turned off and the lower FET is turned on allowing the current to ramp down in the inductor. The

lower FET remains on until the clock initiates another PWM cycle. Figure 54 shows the typical operating waveforms during

PWM operation. The dotted lines illustrate the sum of the current sense and slope compensation signal.

The output voltage is regulated as the error amplifier varies VCOMP1 with changes to the output inductor current. The

error amplifier is a transconductance type, and its output (COMP1) is terminated with a series RC network to GND.

This termination is internal (150k/54pF) if the COMP1 pin is tied to VCC1. In addition, the transconductance for

COMP1 = VCC1 is 50µA/V versus 230µA/V for external RC connection. The non-inverting input of the error amplifier

is internally connected to a 600mV reference voltage, and its inverting input is connected to the output voltage from

the FB1 pin and its associated divider network.

Figure 54. PWM Operation Waveforms

4.5

Light Load Operation

At light loads, converter efficiency can be improved by enabling Pulsed Frequency Modulation (PFM). Connecting

the SYNC pin to GND allows the controller to choose PFM operation automatically when the load current is low.

Figure 55 on page 22 shows the DCM operation. The IC enters the DCM mode of operation when eight

consecutive cycles of inductor current crossing zero are detected. This corresponds to a load current equal to 1/2

the peak-to-peak inductor ripple current and set by Equation 4:

where D = duty cycle, fSW= switching frequency, L = inductor value, IOUT = output loading current, and

VOUT = output voltage.

While operating in PFM mode, the regulator controls the output voltage with a simple comparator and pulsed FET

current. A comparator signals the point at which FB is equal to the 600mV reference at which time the regulator

begins providing pulses of current until FB is moved above the 600mV reference by 1%. The current pulses are

VCOMP

VCSA

Duty

Cycle

IL

VOUT

IOUT

VOUT 1D

–

()

2LfSW

-----------------------------------

=

(EQ. 4)