DSPIC30F datasheet(159/248 Pages) MICROCHIP

159 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 157

dsPIC30F

20.2.2

OSCILLATOR START-UP TIMER

(OST)

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator

Start-up Timer is included. It is a simple 10-bit counter

that counts 1024 T

OSC cycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as T

OST. The TOST time is involved

every time the oscillator has to restart (i.e., on POR,

BOR and wake-up from Sleep). The Oscillator Start-up

Timer is applied to the LP oscillator, XT, XTL, and HS

modes (upon wake-up from Sleep, POR and BOR) for

the primary oscillator.

20.2.3

LP OSCILLATOR CONTROL

Enabling the LP oscillator is controlled with two

elements:

The current oscillator group bits COSC<2:0>.

The LPOSCEN bit (OSCON register).

The LP oscillator is on (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

• COSC<2:0> = 00 (LP selected as main oscillator)

and

• LPOSCEN = 1

Keeping the LP oscillator on at all times allows for a fast

switch to the 32 kHz system clock for lower power oper-

ation. Returning to the faster main oscillator will still

require a start-up time

20.2.4

PHASE LOCKED LOOP (PLL)

The PLL multiplies the clock which is generated by the

primary oscillator. The PLL is selectable to have either

gains of x4, x8, and x16. Input and output frequency

ranges are summarized in Table 20-3.

TABLE 20-3:

PLL FREQUENCY RANGE

The PLL features a lock output which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read only LOCK bit in the OSCCON register.

20.2.5

FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (8 MHz nominal) internal

RC oscillator. This oscillator is intended to provide

reasonable device operating speeds without the use of

an external crystal, ceramic resonator, or RC network.

The FRC oscillator can be used with the PLL to obtain

higher clock frequencies.

The dsPIC30F operates from the FRC oscillator when-

ever the current oscillator selection control bits in the

OSCCON register (OSCCON<14:12>) are set to ‘001’.

The four bit field specified by TUN<3:0> (OSCON

<15:14> and OSCON<11:10>) allows the user to tune

the internal fast RC oscillator (nominal 8.0 MHz). The

user can tune the FRC oscillator within a range of

+10.5% (840 kHz) and -12% (960 kHz) in steps of

1.50% around the factory-calibrated setting, see

Table 20-4.

If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are

set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier

of 4, 8 or 16 (respectively) is applied.

TABLE 20-4:

FRC TUNING

PLL

Multiplier

OUT

4 MHz-10 MHz

16 MHz-40 MHz

4 MHz-10 MHz

32 MHz-80 MHz

4 MHz-7.5 MHz

x16

64 MHz-160 MHz

Note:

When a 16x PLL is used, the FRC fre-

quency must not be tuned to a frequency

greater than 7.5 MHz.

TUN<3:0>

Bits

FRC Frequency

0111

+ 10.5%

0110

+ 9.0%

0101

+ 7.5%

0100

+ 6.0%

0011

+ 4.5%

0010

+ 3.0%

0001

+ 1.5%

0000

Center Frequency (oscillator is

running at calibrated frequency)

1111

- 1.5%

1110

- 3.0%

1101

- 4.5%

1100

- 6.0%

1011

- 7.5%

1010

- 9.0%

1001

- 10.5%

1000

- 12.0%

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