DSPIC30F datasheet(161/248 Pages) MICROCHIP

161 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 159

dsPIC30F

If clock switching is disabled, then the FOS<2:0> and

FPR<4:0> bits directly control the oscillator selection

and the COSC<2:0> bits do not control the clock selec-

tion. However, these bits will reflect the clock source

selection.

20.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

20.3

Reset

The dsPIC30F differentiates between various kinds of

Reset:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during Sleep

Watchdog Timer (WDT) Reset (during normal

operation)

Programmable Brown-out Reset (BOR)

RESET

Instruction

Reset caused by trap lockup (TRAPR)

Reset caused by illegal opcode or by using an

uninitialized W register as an address pointer

(IOPUWR)

Different registers are affected in different ways by var-

ious Reset conditions. Most registers are not affected

by a WDT wake-up since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

situations, as indicated in Table 20-5. These bits are

used in software to determine the nature of the Reset.

A block diagram of the On-Chip Reset Circuit is shown

in Figure 20-2.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internally generated Resets do not drive MCLR pin low.

FIGURE 20-2:

RESET SYSTEM BLOCK DIAGRAM

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 KHz when the fail-safe clock monitor is

enabled.

such

clock

switching

performed, the device may generate an

oscillator fail trap and switch to the Fast RC

oscillator.

Byte Write “0x46” to OSCCON low

Byte Write “0x57” to OSCCON low

Byte Write

“0x78” to OSCCON high

Byte Write

“0x9A” to OSCCON high

MCLR

DD Rise

Detect

POR

SYSRST

Sleep or Idle

Brown-out

Reset

BOREN

RESET

Instruction

WDT

Module

Digital

Glitch Filter

BOR

Trap Conflict

Illegal Opcode/

Uninitialized W Register

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