HIP0080, HIP0081

FN3018 Rev 5.00

Page 9 of 14

November 2000

Dissipation In Multiple Outputs

The HIP0080 and HIP0081 Power Drivers have multiple MOS

Output Drivers and require special consideration with regard to

maximum current and dissipation ratings. While each output

has a maximum current specification consistent with the device

structure, all such devices on the chip can not be

simultaneously rated to the same high level of peak current.

The total combined current and the dissipation on the chip

must be adjusted for maximum allowable ratings, given

simultaneous multiple output conditions.

For the HIP0081, the maximum positive output current rating is

2.2A when one output is ON. When ALL outputs are ON, the

rating is reduced to 1.5A because the total maximum current is

limited to 6A. For any given application, all output drivers on a

chip may or may not have a different level of loading. The

discussion here is intended to provide relatively simple methods

to determine the maximum dissipation and current ratings as a

general solution and, as a special solution, when all switched

ON outputs have the same current loading.

General Solution

A general equation for dissipation should specify that the total

power dissipation in a package is the sum of all significant

elements of dissipation on the chip. However, in Power BiMOS

Circuits very little dissipation is needed to control the logic and

predriver circuits on the chip. The overall chip dissipation is

primarily the sum of the I2R dissipation losses in each channel

where the current, I is the output current and the resistance, R

is the NMOS channel resistance, rDS(ON) of each output

driver. As such, the total dissipation, PD for n output drivers is:

This expression sums the dissipation, Pk of each output driver

without regard to uniformity of dissipation in each MOS

channel. The dissipation loss in an NMOS channel is given in

Equation 2 where the current, I, is determined by the output

load when the channel is turned ON. The channel resistance,

rDS(ON) is a function of the circuit design, level of gate voltage

and the chip temperature. Other switching losses may include

I2R lost in the interconnecting metal on the chip and bond

wires of the package.

The temperature rise in the package due to the dissipation is

the product of the dissipation, PD and the thermal resistance,

JC of the package (Junction-to-Case). To determine the chip

junction temperature, TJ, given the case (heat sink tab)

temperature, TC, the linear heat flow solution is:

or:

Since this solution relates only to the package, further

consideration must be given to a practical heat sink. The

equation of linear heat flow assumes that the thermal

resistance from Junction-to-Ambient (

JA) is the sum of the

thermal resistance from Junction-to-Case and the thermal

resistance from Case (heat sink)-to-Ambient. The Junction-to-

Ambient thermal resistance,

JA is the sum of all thermal paths

from the chip junction to the ambient temperature (TA)

environment and can be expressed as:

The Junction-to-Ambient equivalent to Equation 3, 3A is:

FIGURE 4. SINGLE PULSE ENERGY TEST SHOWING THE

FAILURE BOUNDARY FOR EACH HIP0080

OUTPUT STRESSED TO POINT OF FAILURE

FIGURE 5. SINGLE PULSE ENERGY TEST SHOWING THE

FAILURE BOUNDARY FOR EACH HIP0081

OUTPUT STRESSED TO POINT OF FAILURE

0.1

1

10

100

1000

100

1000

10000

PULSE WIDTH TIME (ms)

HIP0080 SINGLE PULSE

TAMB = 25oC

SA

FE

OP

ER

AT

IN

G

AR

EA

ENERGY vs TIME

NOTE: SAFE OPERATING AREA

BELOW DOTTED LINE

0.1

1

10

100

1000

100

1000

10000

PULSE WIDTH TIME (ms)

HIP0081 SINGLE PULSE

TAMB = 25oC

ENERGY vs TIME

NOTE: SAFE OPERATING AREA

BELOW DOTTED LINE

D

Pk

k1

=

n



=

(EQ. 1)

Pk

I

2

rDS ON





=

(EQ. 2)

TJ

TC PD JC



+

=

(EQ. 3)

(EQ. 3A)

TC

TJ PD JC



–

=

JA JC CA

+

=

(EQ. 4)

TJ

TA PD JA



+

=

(EQ. 5)