20

105 Hardware Specifications

Preliminary/Subject to Change without Notice

1.6 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC105 PCI Bridge/Memory Controller.

1.6.1 PLL Configuration

The MPC105 is designed to operate over a wide range of processor and PCI bus frequencies. The PLL is

configured by the PLL_CFG0–PLL_CFG3 pins. For a given SYSCLK (bus) frequency, the PLL

configuration pins set the internal MPC105 frequency of operation. Table 10 describes the PLL

configurations required for different ratios between the processor bus frequency and the PCI bus frequency.

Table 10. PLL Configuration

Notes:

1. Some PLL configurations may select bus, CPU, or PLL frequencies which are not useful, not

supported, or not tested for by the MPC105. PLL frequencies (shown in parenthesis in Table 10)

should not fall below 120 MHz, and should not exceed 200 MHz.

2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, and the

bus is set for 1:1 mode operation. The PLL-bypass mode is for test only, and is not intended for

functional use. In clock-off mode, no clocking occurs inside the MPC105 regardless of the

SYSCLK input.

3. The PLL_CFG0–PLL_CFG1 signals select the CPU-to-bus ratio (1:1, 2:1) and the

PLL_CFG2–PLL_CFG3 signals select the PCI-to-PLL multiplier (x2, x4, x8).

4. The level 2 cache and memory interfaces will function at the processor bus frequency.

1.6.2 PLL Power Supply Filtering

The AVdd power signal is provided on the MPC105 to provide power to the clock generation phase-lock

loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered

using a circuit similar to the one shown in Figure 12. The circuit should be placed as close as possible to the

AVdd pin to ensure it filters out as much noise as possible.

PLL_CFG0–PLL_CFG3

Processor Bus, PCI, and PLL Frequencies

Processor Bus:

PCI Bus Ratio

(SYSCLK)

PCI Bus

16.6 MHz

PCI Bus

20 MHz

PCI Bus

25 MHz

PCI Bus

33.3 MHz

0001

1:1

—

—

—

33.3

(133)

0010

1:1

16.6

(133)

20

(160)

25

(200)

—

0100

2:1

—

—

—

66.6

(133)

0101

2:1

33.3

(133)

40

(160)

50

(200)

—

0011

PLL bypass

1111

Clock off

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

AR

CH

IVE

D B

Y F

RE

ES

CA

LE

SE

MI

CO

ND

UC

TO

R,

INC

.