CS5320 datasheet(68/160 Pages) AMCC

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S5320 – PCI Match Maker: Operation Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Table 32 describes one of the four configuration registers. All four region configuration registers are exactly the

same.

Table 32. Pass-Thru Configuration Register

Bit

Description

PTADR# mode. This bit is only valid in Active mode. If this bit is 0, PTADR# is not driven at the beginning of an

active cycle. If this bit is set to 1 (default state), the S5320 will assert PTADR# for one clock cycle after PTATN#

is asserted. The Pass-Thru address is also driven while PTADR# is low. This bit is a don’t care if the device is

operating in Passive mode.

Endian conversion. If this bit is set to one, the S5320 will convert the Add-On bus from the default little endian

format to a big endian format. Reference Chapter 9 for more details.

Write FIFO disabled. If this bit is set to 1, the S5320 will not accept the next piece of data (on a PCI write) until

the Add-On has accepted the previous piece of data. If this bit is set to 0, the S5320 will accept data from the

PCI until the Pass-Thru write FIFO is full.

4:3

Prefetch. These bits control the number of DWORDs the S5320 will prefetch after the current PCI Pass-Thru

read completes. The actual amount of data prefetched depends upon any number of different scenarios. The

prefetch values of “small”, “medium” and “large” are available to tune the system to achieve best overall perfor-

mance (i.e., optimize PCI bus transfers or optimize Add-On bus transfers). The Pass-Thru read FIFO can be

enabled to prefetch in either Active mode or Passive mode.

2:0

Wait states. In Active mode, the user can program the number of wait states required by the Add-On bus to com-

plete a transaction. Up to 7 wait states can be programmed (per region). The S5320 will count the number of

clocks programmed into this register before finishing the current data transaction if PTWAIT# is high. If

PTWAIT# is driven low, additional wait states may be inserted. Bits 2, 1 and 0 are don’t care if operating in Pas-

sive mode.

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