CS5320 datasheet(95/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Bus Protocol

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

Data Sheet

Figure 48. Target Disconnect Example 2

Target Aborts

A target abort termination represents an error condi-

tion when no number of retries will produce a

successful target access. A target abort is uniquely

identified by the target deasserting DEVSEL# and

TRDY# while STOP# is asserted. When a target per-

forms an abort, it must also set bit 11 of its PCI Status

target abort when accessed. Target termination types

are summarized in Table 42.

Target Latency

The PCI specification requires that a selected target

relinquish the bus should an access to that target

require more than eight PCI clock periods (16 clocks

for the first data phase, 8 clocks for each subsequent

data phase). This prevents slow target devices from

potentially monopolizing the PCI bus and also allows

more accurate estimations for bus access latency.

Note that a special mode is available to the user which

will allow for this mechanism to be disabled, thus vio-

lating the PCI 2.1 Specification. If a value of 0 is

programmed into the serial nvRAM location 45h, bit 0,

target latency is ignored. In this case, the S5320 will

never issue a retry/disconnect in the event of a slow

Add-On device. This programmable bit is only pro-

vided for flexibility, and most users should leave this bit

set to 1.

nvRAM Location 45h, bit 0 = 0: No disconnect for slow

Add-On device.

nvRAM Location 45h, bit 0 = 1: PCI 2.1 compliant

Target Locking

It is possible for a PCI bus master to obtain exclusive

access to a target (“locking”) through use of the PCI

bus signal LOCK#. LOCK# is different from the other

PCI bus signals because its ownership may belong to

any bus master, even if it does not currently have own-

ership of the PCI bus. The ownership of LOCK#, if not

already claimed by another master, may be achieved

by the current PCI bus master on the clock period fol-

lowing the initial assertion of FRAME#. Figure 50

describes the signal relationship for establishing a

lock. The ownership of LOCK#, once established, per-

sists even while other bus masters control the bus.

Ownership can only be relinquished by the master

which originally established the lock.

PCI Bus Access Latency Components

Figure 49. Target-Initiated Retry

FRAME#

IRDY#

TRDY#

DEVSEL#

ST OP#

PCLK

(I)

(T)

(I) Driven by Initiator

(T) Driven by Target

(I)

(T)

Data

Transfered

Target

Disconnect

Single

Data

Transferred

Bus Access Latency

REQ#

Asserted

GNT#

Asserted

FRAME#

Asserted

TRDY#

Asserted

--Arbitration Latency-- --Bus Acquisition--

Latency

--Target Latency--

FRAME#

IRDY#

TRDY#

DEVSEL#

STOP#

PCLK

(I)

(T)

(I) Driven by Initiator

(T) Driven by Target

(I)

(T)

Target Retry

Signaled

Initiator

Sequences IRDY#

+ FRAME# to return

to IDLE state

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