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ADIS16080/PCBZ Datasheet(PDF) 5 Page - Analog Devices |
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ADIS16080/PCBZ Datasheet(HTML) 5 Page - Analog Devices |
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5 / 16 page  ADIS16080 Rev. 0 | Page 5 of 16 TIMING SPECIFICATIONS TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1 Table 2. Parameter VCC = VDRIVE = 5 Unit Description fSCLK2 10 kHz min 20 MHz max tCONVERT 16 × tSCLK tQUIET 50 ns min Minimum quiet time required between CS rising edge and start of next conversion t2 10 ns min CS to SCLK setup time t33 30 ns max Delay from CS until DOUT three-state disabled t43 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t7 10 ns min SCLK to DOUT valid hold time t84 15/35 ns min/max SCLK falling edge to DOUT high impedance t9 10 ns min DIN setup time prior to SCLK falling edge t10 5 ns min DIN hold time after SCLK falling edge t11 20 ns min 16th SCLK falling edge to CS high t12 1 μs max Power-up time from full power-down/auto shutdown modes 1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 V × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 1 2 3 4 5 6 11 12 13 14 15 16 B SCLK DOUT DIN CS ZERO ADD1 ADD0 DB11 DB10 DB4 DB3 DB2 DB1 DB0 LOW WRITE DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC 2 IDENTIFICATION BITS ZERO THREE-STATE THREE-STATE t2 t3 t4 t9 t6 t7 t10 tCONVERT t5 t8 t11 tQUIET Figure 2. Gyroscope Serial Interface Timing Diagram 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 3. Load Circuit for Digital Output Timing Specifications |
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