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ADIS16080/PCBZ Datasheet(PDF) 12 Page - Analog Devices

Part # ADIS16080/PCBZ
Description  짹80째/sec Yaw Rate Gyro with SPI Interface
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16080/PCBZ Datasheet(HTML) 12 Page - Analog Devices

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ADIS16080
Rev. 0 | Page 12 of 16
CONTROL REGISTER
The control register on the ADIS16080 is a 12-bit, write-only
register. Data is loaded from the DIN pin on the falling edge of
SCLK. The data is transferred on the DIN line at the same time
that the conversion result is read from the part. The data
transferred on the DIN line dictates the configuration for the
next conversion.
This requires 16 serial clocks for every data transfer. Only the
information provided on the first 12 falling clock edges (after
CS falling edge) is loaded to the control register.
MSB denotes the first bit in the data stream. The DIN Bit
Stream bit map shows the analog input channel selection
options.
Table 5. Channel Selection
Analog Input Channel
ADD1
ADD0
Gyroscope
0
0
Temperature Sensor
0
1
AIN1 Input
1
0
AIN2 Input
1
1
DIN Bit Stream
MSB (11)
LSB (0)
WRITE
LOW
DONTC
DONTC
ADD1
ADD0
HIGH
HIGH
DONTC
DONTC
LOW
CODING
Table 6. Analog Input Channel Selection Options
Bit
Mnemonic
Comment
s
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register or not. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the
remaining 11 bits are not loaded to the control register, and it remains unchanged.
10
LOW
This bit should be low.
9, 8
DONTC
Don’t care.
7, 6
ADD1, ADD0
These two address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted in the next serial transfer. The selected input channel is decoded as shown in Table 5.
The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next
channel to be converted is selected by the mux on the 14th SCLK falling edge.
5, 4
HIGH
These bits should be high.
3, 2
DONTC
Don’t care.
1
LOW
This bit should be low.
0
CODING
This bit selects the type of output coding used for the conversion result. If this bit is set to 0, the output coding for
the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next
conversion).



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