ADIS16080

Rev. 0 | Page 13 of 16

SERIAL INTERFACE

Figure 2 shows the detailed timing diagram for the serial

interface to the ADIS16080. The chip select signal, CS, frames

the entire data transfer, because it must be kept in a Logic 0

state to communicate with the ADIS16080. The serial clock,

SCLK, provides the conversion clock and controls the transfer

of information to and from the ADIS16080 during each

conversion cycle. The data input, DIN, provides access to

critical control parameters in the control register; and the

output signal, DOUT, provides access to the ADIS16080

output data.

The ADIS16080 offers an efficient data transfer function by

supporting simultaneous READ and WRITE cycles. A data

transfer cycle is started when the CS transitions to a Logic 0

state. If DIN is in a Logic 1 state during the first falling edge of

the SCLK, then the next 11 SCLK cycles fill the control register

with the contents on the DIN pin. The appropriate bit defini-

tions for DIN can be found in the DIN Bit Stream bit map and

Table 6. If DIN is in a Logic 0 state during the first falling edge

of the SCLK, then the contents of the control register remain

unchanged. Because the control register is only 12 bits wide,

the contents on the DIN pin during the last four SCLK cycles

are ignored.

During this same cycle, the digital output data is clocked out on

the DOUT pin. The 12 bits of data are preceded by two leading

0s and two channel address bits, ADD1 and ADD0, identifying

to which channel the result corresponds (see the Reading DOUT

Bit Stream bit map and Table 7).

CS going low clocks out the first leading zero to be read in by

the system microcontroller or DSP on the first falling edge of

SCLK. The first falling edge of SCLK will also clock out the

second leading zero to be read in by the microcontroller or DSP

on the second SCLK falling edge, and so on.

The remaining two address bits and 12 bits are then clocked out

by subsequent SCLK falling edges, beginning with the first

address bit, ADD1; thus, the second falling clock edge on the

serial clock has the second leading 0 provided and also clocks

out Address Bit ADD1. The final bit in the data transfer is valid

on the 16th falling edge, having been clocked out on the previous

(15th) falling edge.

After the 16th falling edge of SCLK, the DOUT line goes back

into a three-state mode. If the rising edge of CS occurs before

16 SCLKs have elapsed, the DOUT line goes back into three-

state mode and the control register is not updated. Otherwise,

DOUT returns to a three-state mode on the 16th SCLK falling

edge, as shown in Figure 2.

For the analog inputs, the CS signal initiates the data transfer

and conversion process. The falling edge of CS put the track and

hold into hold mode and takes the bus out of the three-state.

The analog input is sampled at this point. The conversion is also

initiated at this point and requires 16 SCLK cycles to complete.

Reading DOUT Bit Stream

Table 7. DOUT Bit Functions

SCLK

Mnemonic

Comment

s

1, 2

LOW

The outputs are low for SCLK1 and SCLK2.

3, 4

ADD1, ADD0

The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data.

See Table 5 for the coding of these address bits.

5

DB11

Data Bit 11 (MSB).

6 to 15

DB10 to DB1

Data Bit 10 to Data Bit 1.

16

DB0

Data Bit 0 (LSB).

SCLK1

SCLK16

LOW

LOW

ADD1

ADD0

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0